Over the last twenty years, integrated circuit fabrication technology has progressed so that high performance devices can be fabricated in volume production. Many features have been incorporated into the process to achieve high performance, high density and high reliability. Additionally, process features have been added to increase capabilities such as implants for capacitors and special gate oxides for transistors with multiple threshold voltage values. In some cases, process steps have been included to enable the fabrication of memories in CMOS processes. While these additions have significantly improved the performance of integrated circuits and CMOS devices in particular, these additions to manufacturing processes have also caused the cost of production to increase substantially.
Going back several IC process generations, it can be seen that some of the modern process features were not available, while others were not needed to achieve performance and reliability specifications for the devices of the time. As process features scaled down, however, and the switch to CMOS technology (rather than NMOS technology) was made, the speed of the circuitry increased dramatically. These performance improvements and speed requirements caused changes to occur in CMOS processes. For example, the base CMOS process outpaced the interconnect technology and exposed the series resistance of transistor regions as a significant problem. Additionally, the high performance of the transistors tended to cause degradation of the devices, particularly in the gate oxide due to hot carrier injection. Many additional process features, therefore, were targeted at improving the parameters outside of the transistor channel. For example, the series resistance of the gate electrode and the resistance of the source/drain junctions were targeted with silicide or salicide processes that could decrease resistances by an order of magnitude. Transistor parameters were also adjusted. For example, as transistor channel lengths decreased substantially, large amounts of hot carriers began to be generated in normal operation. These hot carriers were injected into the gate oxide with a portion of them becoming trapped in the gate oxide, often resulting in an increase in the threshold voltage of the transistor. This increase of threshold voltage reduced the performance of the device. A process called lightly-doped-drain (LDD) then became a common additional process step to CMOS processing. This LDD process step was used to reduce hot carrier generation and to prevent transistor degradation. Still further, the density of signals and the density of power forced the use of more metal layers to meet those demands. Thus, multiple levels of metal interconnects were added to increase the density of interconnections. In short, CMOS processes have over the years come to include a variety of process complexities to counteract problems brought on by smaller, higher performance CMOS devices.
In most cases for fabrication facilities today, and particularly for micron and sub-micron device geometries, CMOS processes have become standardized and have specific design rules that must be met by designers who are designing for these CMOS processes. In addition, many integrated circuit design companies today do not have their own fabrication facilities, but rather rely upon manufacturing services and standard manufacturing processes provided by third-party suppliers, such as TSMC (Taiwan Semiconductor Manufacturing Company). For companies that do have their own fabrication facilities, it is still often the case that the manufacturing processes are first defined, and then new devices are developed and designed subject to the defined design rules for those processes. As such, device designers, in general, seek to take advantage of the various capabilities of standard CMOS processes by maximizing the features and/or operating ranges for the devices being designed.
Radio frequency identification (RFID) devices are devices that are typically powered by collecting RF energy and rectifying the waveform to create a DC power supply. The RF energy is typically generated by a reader system that interrogates the RFID device by transmitting an RF signal at a selected frequency, or within a frequency range, with respect to which the RFID device has been designed to respond. The RF interrogation signal can contain commands to communicate with the RFID device, so that the exact “identity” of the chip can be determined by the transmitter. Often RFID tag circuitry includes integrated circuitry that is connected to an antenna in the surrounding package material. And current efforts are being made to bring this antenna on to the chip itself.
There are a wide variety of applications within which RFID systems can be utilized. For example, manufacturing and sales channel applications are currently being targeted as likely industries within which RFID technology could provide significant advantages. This RFID technology, therefore, has the potential of being an extremely high volume integrated circuit (IC) application compared to many ICs in production today. One of the biggest barriers for the universal implementation of such RFID technology today, however, is the device cost for the RFID tags themselves. As such, there is a desire in the RFID industry to reduce the cost of each RFID tags to about five cents. It is believed that if such a low-cost solution could be achieved, the barrier to entry for companies desiring to implement RFID systems would be significantly reduced such that RFID tags would begin to be placed on a large portion of goods that are manufactured and sold. Although some focus has been applied to CMOS processing technologies to solve the problem of making a low-cost RFID tag, a viable and efficient CMOS process solution has yet to be adequately identified or achieved.